A metal-oxide-semiconductor (MOS) field effect transistor (FET) comprises a gate electrode separated from a semiconductor substrate by a gate dielectric which is above a channel region in the substrate. A source region and a drain region are located at the ends of the channel region. The “ON” or “OFF” states of the transistor is controlled by the voltage applied at the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrodes to isolate the gate electrode from the source/drain (S/D) contacts. The parasitic capacitance between the gate and the S/D contacts adversely affects the transistor performance. As CMOS transistor feature sizes are shrunk, the sidewall spacer thickness is reduced as well, resulting in increased degradation of device performance due to the parasitic capacitance. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.